1. Field of the Invention
This invention relates to electronic circuits and semiconductor devices that will receive light and convert the light to an electronic signal representing the amplitude of the light commonly referred to as photo-sensors or pixel sensors. More particularly this invention relates to methods and apparatus for testing light sensing devices, circuits, and blocks. This invention further identifies the use of such DFT methods and apparatus for testing of functionality and manufacturing process values to assure the operation of photosensors or pixel sensors in providing reliable and accurate electronic shuttering of captured light information as an array of pixels. This invention especially relates to methods and apparatus for testing of circuits and blocks known as active pixel sensors (APS).
2. Description of Related Art
Imaging circuits typically include a two dimensional array of photo-sensors. Each photo-sensor comprises one picture element (pixel) of the image. Light energy emitted or reflected from an object impinges upon the array of photo-sensors The light energy is converted by the photo-sensors to an electrical signal. Imaging circuitry scans the individual photo-sensors to readout the electrical signals. The electrical signals of the image is processed by external circuitry for subsequent display.
Modern metal oxide semiconductor (MOS) design and processing techniques have been developed that provide for the capture of light as charge and the transporting of that charge within APS and other structures so as to be accomplished with almost perfect efficiency and accuracy.
U.S. Pat. No. 5,841,126 (Fossum, et. al.) describes a CMOS active pixel sensor (APS) type imaging system on a chip. The imaging system consists of an APS and a controller on a single substrate. The controller provides specialized support electronics that are integrate onto the same substrate as the APS array. The controller includes integration, timing, control electronics, signal chain electronics, A/D Conversion, and other important control systems.
U.S. Pat. No. 5,900,623 (Tsang, et. al.) describes an active pixel sensor implemented with CMOS technology that employs an array of photocells. Each cell includes a photodiode to sense illumination and a separate storage node with a stored charge that is discharged during an integration period by the photocurrent generated by the photodiode. Each photocell includes a switching network that couples the photocurrent to the storage node only during the integration period while ensuring that a relatively constant voltage is maintained across the photodiode during integration and non-integration periods.
While the prior art patents describe the system, circuitry, functioning, and timing of pixel circuits and APS. None of the patents include any aspects of testing apparatus and methods for testing functionality, evaluating performance or determining capacitance of an APS.
FIG. 1 shows a typical CMOS Active Pixel Sensor (APS) of the prior art, using a photo-diode as a photo-conversion device for example. The drain terminals of the transistors M1 and M2 are connected to the power supply voltage distribution line, VDD. The source of the transistor M2 is connected to the anode of the photo-diode DF. The cathode of the photo-diode is connected to the ground reference point. The capacitance CFD is the inherent capacitance of the photo-diode DF.
The gate of the transistor M2 is connected to a reset terminal to receive the reset signal Vrst. The sensor readout node FD, that is the anode of the photo-diode DF, is first reset to a high voltage level (VDD) by changing the reset signal Vrst from a low voltage level (0) to a high voltage level (VDD) to charge the capacitance CFD. At the completion of charging the capacitance CFD, the reset signal Vrst is changed from the high voltage level (VDD) to the low voltage level. Since light is shown on the photo-diode DF, photo-generated electrons are collected at node FD and the voltage at the node FD decreases in the process. At the end of the exposure duration the voltage at node FD is measured, thus completing one photo-sensing cycle. The photo-sensing cycle is completed by deactivating the transistor M3 by changing the row select signal from the high voltage level (VDD) to the low voltage level (0).
The gate of the transistor M1 is connected to the node FD and the source of the transistor M1 is connected to the drain of the transistor M3. The transistor M1 acts as a source follower such that the voltage present at the source of the transistor M1 xe2x80x9cfollowsxe2x80x9d directly the voltage present at the gate of the transistor M1 and is one transistor threshold voltage VT below the voltage present at the gate of the transistor M1.
The gate of the transistor M3 is connected to the row select line to receive the row select signal Vrow. The source of the transistor M3 is connected to the column bus ColBus. The column bus interconnects all the APS""s present on a column of an array of APS""s. When the row select signal changes from a low voltage level (0V) to a high level (VDD), the transistor M3 turns-on and the voltage present at the source of the transistor M1 is transferred to the output of the APS to couple the voltage that is proportional to the intensity of the light L. The output signal Voutxe2x80x94pixel of the APS is coupled to the column bus ColBus for further conditioning and readout.
An APS signal conditioning and readout circuit as shown in FIG. 2 and described in Fossum, et. al. is connected to the column bus ColBus of each column of APS""s of an array of APS""s. The APS signal and readout circuit employs correlated double sampling (CDS) to determine the level of the light L impinged upon the photodiode Df. Correlated double sampling (CDS) is achieved by sampling both a reset reference level and a signal level. The difference between the signal level and the reset reference level represents the net signal induced by level of the light L illuminating the photodiode DF. The resulting voltage of the node FD is read out through the transistors M1 and M3 of the APS pixel circuit of FIG. 1 onto the column bus ColBus. The voltage Voutxe2x80x94pixel on the column bus ColBus is sampled onto a first holding capacitor C1 by an activation pulse SHR to the gate of the transistor M6. This initial charge is used as the baseline. After raising the reset signal Vrst, the signal charges within the APS pixel circuit due to the impinging of photoelectrons and the capacitance CFD. The resulting voltage Voutxe2x80x94pixel is also transferred onto the column bus ColBus and sampled onto a second holding capacitor C2 by an activation pulse SHS to the gate of the transistor M5. The difference between the voltages on the first capacitor C1 and the second capacitor C2 is therefore indicative of the number of photoelectrons of the light L that were allowed to enter the photodiode Df.
A key element in the calculation of the conversion gain in a CMOS APS imager pixel is the measurement of the capacitance CFD at the pixel readout node, FD.
In the prior art, a conventional APS test scheme used to measure the capacitance is shown in FIG. 3. To summarize how such an APS test approach is used, a photo-diode pixel of FIG. 1 is used as an example.
The structure of FIG. 1 is modified such that the drain connections of the transistors M1 and M2 are separately connected. The drain of M1 is now connected to the supply line, VDD1, while the drain of M2 is connected to another supply line, VDD2.
The voltage source VS1 driving the supply line VDD1 is set to a voltage level of the power supply voltage source VDD. A second voltage source connected to the VDD2 line is also set to the same value, the power supply voltage source VDD. Bright light is shown on the pixel so that it is saturated. The reset signal Vrst is pulsed periodically and the resulting average current from the voltage source is measured. The equation relating the measured average current I and the capacitance CFD on the node FD of the photo-diode DF is calculated by the formula:
I=dQ/dt=QFD*dV/dtxe2x80x83xe2x80x83Eq. 1
where:
dt is the period of the reset signal Vrst 
dV is the voltage difference between reset level and saturation level.
The capacitance is therefore:                               C          FD                =                  I                                    ⅆ              V                                      ⅆ              t                                                          Eq        .                  xe2x80x83                ⁢        2            
Although the electrical design of the APS pixel test approach shown in FIG. 2 is similar to the one shown in FIG. 1, the physical layout of the two pixels are quite different. In a normal pixel design, in order to increase the density of the pixels per unit area of the APS""s and to reduce the complexity of signal routing, the drains of M1 and M2 are connected together to the same supply, VDD, through a single metal line.
However in the APS cell test approach of the prior art, since the drain connections of transistors M1 and M2 in FIG. 3 need to be separated in order to facilitate the above test measurement, two metal lines are needed to route the two drain connections. As a result, the pixel design is less area efficient than a design that includes no special test circuitry.
In the design approach for imaging products using arrays of APS cells, in actual application, it is preferred that the more efficient pixel in FIG. 1 is used. In order to measure the conversion gain of the pixel design implemented using a particular semiconductor manufacturing process, an additional row of the pixel cells implemented using an approach such as shown in FIG. 3 needs to be added to the normal APS pixel array.
In addition, in a conventional APS array embodiment, the additional row of testable APS pixels cannot be covered up by light shielding material to form part of the xe2x80x9cdark pixelsxe2x80x9d normally placed around the active pixels since they must operate under bright light for the measurement
It is an objective of this invention is to provide an apparatus for testing an active pixel sensor to ensure that a signal proportional to the quantity of light energy impinging on the active pixel sensor is reliably and accurately captured and made available for further on processing the rest of the APS system circuitry.
It is another objective of this invention is to provide a method and apparatus for determining the capacitance of a photo-conversion device of the active pixel sensor.
Further, it is an object of this invention to provide a method and apparatus for determining that an active pixel sensor is functioning correctly.
Still further, is it is an object of this invention to provide a method and apparatus for determining the performance of an active pixel sensor. Where the performance of the active pixel sensor is a measure of linearity of the active pixel sensor and a connected chain of circuitry that process the signal converted by the photo-conversion device of the active pixel sensor.
To accomplish these and other objectives, an apparatus for testing functionality, evaluating performance and measuring capacitance of a photo-conversion device of at least one active pixel sensor of an array of active pixel sensors has a test voltage selection circuit. The test voltage selection circuit selectively applies any of a plurality of voltage levels that vary incrementally from a first voltage level to a second voltage level to a reference distribution node of the active pixel sensors. The apparatus further has a timing control circuit. The timing control circuit is connected to the test voltage circuit and to the array of active pixel sensors, and to a signal conditioning and readout circuit to provide signals to select timings to select application of the first voltage level and the second voltage level to the reference distribution node of the active pixel sensors, signals at appropriate timings to condition the active pixel sensors in preparation for sensing light impinging upon the array of active pixel sensors, and providing signals for timing the signal conditioning and readout circuit to sense a signal from each active pixel sensor indicating a magnitude of light impinging upon the array of active pixel sensors.
A first embodiment of the test voltage selection circuit includes a first switch. The first switch has a first terminal connected to a first voltage source that provides the first voltage level, a second terminal connected to the reference distribution node of at least one active pixel sensor on a row of active pixel sensors, and a control terminal connected to the controlling circuit to selectively connect and disconnect the first terminal with the second terminal. The test voltage selection circuit has a second switch. The second switch has a first terminal connected to a second voltage source that provides the second voltage level, a second terminal connected to the reference distribution node of at least one active pixel sensor on the row of active pixel sensors in the array of active pixel sensors, and a control terminal connected to the controlling circuit to selectively connect and disconnect the first terminal with the second terminal. The test voltage selection circuit has a current measuring device connected so as to measure a current flowing from the first voltage source.
The timing control circuit enables measurement of the capacitance of the photo-conversion device within one active pixel sensor by selecting the active pixel sensor at a first time. At a second time, the second voltage level is placed at the reference distribution node of the active pixel sensor and simultaneously, at the second time, the second voltage level is coupled to the photo-conversion device. Subsequent to applying the second voltage level to the photo-conversion device, the first voltage level is applied to the reference distribution node at a third time. Simultaneously, at the third time, the first voltage level is coupled to the photo-conversion device. The current flowing to the photo-conversion device to charge the capacitance of the photo-conversion device from the first voltage level to the second voltage level is measured. The capacitance of the photo-conversion device is determined by the formula:       C    FD    =      I                  ⅆ        V                    ⅆ        t            
where
CFD is the total capacitance of the photo-conversion devices and the parasitic capacitance of the test voltage select circuit,
I is the current flowing from the first voltage source,
dv is the difference between the first voltage level and the second voltage level, and
dt is a charging time for the capacitance;
The timing control circuit enables testing functionality of a row of the active pixel sensors within the array of active pixel sensors and the chain of circuitry connecting the selected row of active pixel sensors selecting the row of active pixel sensors at a first time. At a second time, one of the plurality of voltage levels is placed on each reference distribution node of each active pixel sensor. The magnitude of the voltage level placed on each reference distribution node is indicative of a position on the row of active pixel sensors of each active pixel sensor. Simultaneously, at the second time, the voltage level of the plurality of voltage levels is coupled to the photo-conversion device to charge the capacitance of the photo-conversion device to the voltage level. The voltage level of the capacitance of each active pixel sensor on the selected row of active pixel sensors sampled and held the within the signal conditioning and readout circuit at a third time. The first voltage level is placed at the reference distribution node of each active pixel sensor on the row of active pixel sensors at a fourth time. Simultaneously, at the fourth time, the first voltage level is coupled to the capacitance of the photo-conversion device of each active pixel sensor of the row of active pixel sensors. At a fifth time, the first voltage level sampled and held on the capacitance of the photo-conversion device of each active pixel sensor on the selected row of active pixel sensors within the signal conditioning and readout circuit. The sampled and held voltage level of the plurality of voltage levels and the sampled and held first voltage level of each active pixel sensor of the selected row of active pixel sensors are then transferred to an output port of the signal conditioning and readout circuit for transfer to external circuitry. The external circuitry differentially compares the sampled and held voltage level of the plurality of voltage levels with the sampled and held first voltage level and the functionality of each active pixel sensor on the selected row of active pixel sensors, and the chain of circuitry connected to each active pixel sensor of the row of active pixel sensors is determined as a function of a difference between the sampled and held voltage level of the plurality of voltage levels and the sampled and held first voltage level.
The timing and control circuit enables evaluating performance of at least one active pixel sensor and the chain of circuitry connected to the active pixel sensor by selecting the active pixel sensor at a first time. At a second time, the second voltage level is placed at the reference distribution node of the active pixel sensor. Simultaneously, at the second time, the second voltage level is coupled to the capacitance of the photo-conversion device. The second voltage level sampled and held the within the signal conditioning and readout circuit at a third time. At a fourth time, the first voltage level is placed at the reference distribution node of the active pixel sensor and simultaneously, the first voltage level is coupled to the capacitance of the photo-conversion device at the fourth time. At a fifth time, the first voltage level from the capacitance of the photo-conversion device of the active pixel sensor sampled and held to the signal conditioning and readout circuit. The sampled and held first voltage level and the sampled and held second voltage level is transferred to an output of the signal conditioning and readout circuit for transfer to external circuitry. The external circuitry differentially compares the sampled and held first voltage level and the sampled and held second voltage level such that the difference of the sampled and held first voltage level and the sampled and held second voltage level determines performance of the active pixel sensor.
In a second embodiment the test voltage selection circuit has a first voltage distribution line containing a first distribution voltage level and a second voltage distribution line containing a second distribution voltage level. The test voltage selection circuit has a first switch. The first switch has a first terminal connected to a first voltage source that provides the first voltage level, a second terminal connected to the first voltage distribution line, a third terminal connected to the second voltage distribution line, and a control terminal connected to the timing and control circuit to selectively connect the first terminal to the second and third terminals concurrently. The test voltage selection circuit further has a second switch. The second switch has a first terminal connected to a second voltage source that provides the second voltage level, a second terminal connected to the first voltage distribution line, a third terminal connected to the second voltage distribution line, and a control terminal connected to the timing and control circuit to selectively connect the first terminal to the second and third terminals concurrently. The test voltage selection circuit has a third switch. The third switch has a first terminal connected to the first voltage source, a second terminal connected to the second voltage source, a third terminal connected to the first voltage distribution line, a fourth terminal connected to the second voltage distribution line, and a control terminal connected to the timing and control circuit to selectively connect the first terminal to the third terminal and concurrently connect the second terminal to the fourth terminal. Additionally, the test voltage selection circuit has a voltage divider. The voltage divider is connected between the first voltage distribution line, and connected to the reference distribution node of each active pixel sensor on a row of active pixel sensors for the array of active pixel sensors for distributing an incremental voltage level that varies fractionally from the first distributed voltage level present at the first voltage distribution line to the second distributed voltage level present at the second voltage distribution line. The test voltage selection circuit includes a current measuring device connected so as to measure current flowing from the first voltage source.
In the second embodiment of the test voltage selection circuit the timing and control circuit enables measurement of the average capacitance of the photo-conversion device within a group of active pixel sensors of the array of active pixel sensors by selecting the group of active pixel sensors, at a first time. During a period of time between a second time and a third time, the second switch is activated to connect the first terminal of the second switch to the second terminal and third terminal of the second switch to apply the second voltage level to the first and second voltage distribution lines and thus to the reference distribution node of each active pixel sensor of the group of active pixel sensors. Simultaneously, during the period between the second time and the third time, the second voltage level is coupled to the capacitance of the photo-conversion device of each active pixel sensor of the group of active pixel sensors to charge the capacitance to the second voltage level. During a period of time between a fourth time and a fifth time, the first switch is activated to connect the first terminal of the first switch concurrently to the second and third terminals of the first switch to apply the first voltage level to the first and second voltage distribution lines and thus to the reference distribution node of each active pixel sensor of the group of active pixel sensors. Simultaneously, during the period between the fourth and fifth time, the first voltage level is coupled to the capacitance of the photo-conversion device of each active pixel sensor of the group of active pixel sensors to charge the capacitance of the photo-conversion device to the first voltage level. The current flowing from the first voltage source to charge the capacitance of the photo-conversion device of each active pixel sensor of the group of active pixel sensors is then measured. The total capacitance of the photo-conversion devices of the group of active pixel sensors and a parasitic capacitance of the test voltage select circuit is determined by the formula:       C    T    =            I      T                      ⅆ        V                    ⅆ                  t          CT                    
where
CT is the total capacitance of the photo-conversion devices and the parasitic capacitance of the test voltage select circuit,
IT is the current flowing from the first voltage source,
dv is the difference between the first voltage level and the second voltage level, and
dtCT is a charging time for the total capacitance;
The parasitic capacitance is now measured by activating the second switch to connect the first terminal of the second switch to connect the second terminal and third terminal of the second switch to apply the second voltage level to the first and second voltage distribution lines and thus to the reference distribution node of each active pixel sensor of the group of active pixel sensors, during a period of time between a sixth time and a seventh time. The first switch is then activated to connect the first terminal of the first switch concurrently to the second and third terminals of the first switch to apply the first voltage level to the first and second voltage distribution lines and thus to the reference distribution node of each active pixel sensor of the group of active pixel sensors, during a period of time between an eighth time and a ninth time. The current flowing from the first voltage source to charge the parasitic capacitance of the test voltage select circuit is then measured. The parasitic capacitance of the test voltage select circuit is determined by the formula:       C    P    =            I      P                      ⅆ        V                    ⅆ                  t          CP                    
where
CP is the parasitic capacitance of the test voltage select circuit,
IP is the current flowing to the parasitic capacitance CP during charging from the second voltage level to the first voltage level,
dv is a difference between the first voltage level and the second voltage level, and
dtCP is a charging time for the parasitic capacitance,
The average capacitance of the photo-conversion device of each of the active pixel sensors of the group of active pixel sensors is determined by the formula:             C      FD        _    =                    C        T            -              C        P              n  
where
{overscore (CFD)} is the average capacitance of the photodiode,
CT is the total capacitance,
CP is the parasitic capacitance, and
n is a number of active pixel sensors of the group of active pixel sensors.
The second embodiment of the timing and control circuit enables testing functionality of a group of at least one active pixel sensor by, at a first time, selecting the group of active pixel sensors. During a period of time between a second time and a third time, the third switch is activated to apply the first voltage level to the first voltage distribution line and to apply the second voltage level to the second voltage distribution line such that one of the incremental voltage levels is applied to the reference distribution node of each active pixel sensor of the group of active pixel sensors. Simultaneously, during the period between the second and third time, the incremental voltage level is coupled to the capacitance of the photo-conversion device of each active pixel sensor to the row of active is pixel sensors to charge the capacitance of the photo-conversion device to the incremental voltage level. The incremental voltage level present on the capacitance of the photo-conversion device of each of the active pixel sensors of the group of active pixel sensors is sampled and held within the signal conditioning and readout circuit, during a period of time between a fourth time and a fifth time. The first switch is activated to apply the first voltage level to the first voltage distribution line and the second voltage distribution line to place the first voltage level at the reference distribution node of each active pixel sensor of the group of active pixel sensors during a period of time between a sixth time and a seventh time. Simultaneously, during the period of time between the sixth time and the seventh time, the first voltage level is coupled from the reference distribution node to the capacitance of the photo-conversion device of each active pixel sensor of the group of active pixel sensors to charge the capacitance of the photo-conversion device from the incremental voltage level to the first voltage level. The first voltage level present on the capacitance of the photo-conversion device of each active pixel sensor of the group of active pixel sensors is sampled and held within the signal conditioning and readout circuit during a period of time between an eighth time and a ninth time. The sampled and held incremental voltage level present of the capacitance of the photo-conversion device of each of the active pixel sensors of the group of active pixel sensors and the sampled and held first voltage level of each of the active pixel sensors of the group of active pixel sensors are placed at an output port of the signal conditioning and readout circuit for transfer to external circuitry. The external circuitry differentially compares the sampled and held increment voltage level and the first voltage level, thus determining the functionality of each active pixel sensor of the group of active pixel sensors, and the chain of circuitry connected to each active pixel sensor of the group of active pixel sensors is determined as a function of a difference between the sampled and held incremental voltage level and the sampled and held first voltage level.
The timing and control circuit enables evaluating performance of a group of at least one active pixel sensor of the array of active pixel sensors by at a first time, selecting the group of active pixel sensors. Then during a period of time between a second time and a third time, the second switch is activated to apply the second voltage level to the voltage distribution line such that the second voltage level is applied to the reference distribution node of each active pixel sensor of the group of active pixel sensors. Simultaneously, during the period of time between the second and third time, the second voltage level is coupled to the capacitance of the photo-conversion device of each active pixel sensor to the it i row of active pixel sensors to charge the capacitance of the photo-conversion device to the second voltage level. The second voltage level present on the capacitance of the photo-conversion device of each of the active pixel sensors of the group of active pixel sensors is sampled and held within the signal conditioning and readout circuit during a period of time between a fourth time and a fifth time. During a period of time between a sixth time and a seventh time, the first switch is activated to apply the first voltage level to the first voltage distribution line and the second voltage distribution line to place the first voltage level at the reference distribution node of each active pixel sensor of the group of active pixel sensors. Simultaneously, during the period of time between the sixth time and the seventh time, the first voltage level is coupled from the reference distribution node to the capacitance of the photo-conversion device of each active pixel sensor of the group of active pixel sensors to charge the capacitance of the photo-conversion device from the incremental voltage level to the first voltage level. The first voltage level present on the capacitance of each active pixel sensor of the group of active pixel sensors is sampled and held within the signal conditioning and readout circuit during a period of time between an eighth time and a ninth time. The sampled and held second voltage level present on the capacitance of the photo-conversion device of each of the active pixel sensors of the group of active pixel sensors and the sampled and held first voltage level of each of the active pixel sensors of the group of active pixel sensors are placed at an output port of the signal conditioning and readout circuit for transfer to external circuitry. The external circuitry differentially compares the sampled and held second voltage level and the first voltage level, thus determining performance of each active pixel sensor of the group of active pixel sensors and of the chain of circuitry connected to each active pixel sensor of the group of active pixel sensors is determined as a function of a difference between the sampled and held incremental voltage level and the sampled and held first voltage level.
The group of active pixel sensors being tested for functionality, evaluated for performance and having its capacitance measured is usually a row of an array of active pixel sensors. The group of active pixel sensors can be a row of active pixel sensors placed in an area of dark pixels of the array of active pixel sensors at an edge of the array of active pixel sensors.
The evaluating performance of each active pixel sensor of the group of active pixel sensors includes evaluating range and linearity of each active pixel sensor and the chain of circuitry connected to active pixel sensor.